[ The PC Guide | Systems and Components Reference Guide | Motherboard and System Devices | System Cache | Function and Operation of the System Cache ]

The memory address provided by the processor represents which byte of information the processor is looking for at a given time. This is looked at in three sections by the cache controller as it does its work of checking for hits. This example is the same as before (64 MB memory, 512 KB cache, direct mapping to keep things simple) so we again have 26 address bits, A0 through A25:

• A0 to A4: The lowest-order 5 bits represent the 32 different bytes within the data store (2^5 = 32). Recall that the cache we are looking at has 32 byte lines, all of which are moved around together. Therefore, the address bits A0 to A4 are ignored by the cache controller; the processor will use them later to determine which to use of the 32 bytes it receives from the cache.
• A5 to A18: These 14 bits represent the cache line that this address maps to. 2^14 is 16,384, which is the total number of cache lines in our example, as you recall. This cache line address is used for looking up both the tag address in the tag RAM, and later the actual data in the data store if there is a hit.
• A19 to A25: These 7 bits represent the tag address, which tells the system which of the possible memory locations that share the cache line (indicated by address lines A5 to A18) is currently using it.

If the numbers in the example change, so do these ranges. If instead we have 32 MB of memory, 128 KB of cache, and 16 byte cache lines, then A0 to A3 are ignored, A4 to A16 represent the cache line address, and A17 to A24 are the tag address.

Next: Cache Write Policy and the Dirty Bit

Home  -  Search  -  Topics  -  Up